[PhD] Neuro-cellular computing for fault-tolerant reconfigurable hardware
BISCUIT team, Loria
Supervisor : Bernard Girau (HDR)
The development of semiconductor technology has boosted an increasing integration density in current deep-submicron and nano-scale chips. However, as semiconductor manufacturing technology continues towards reduced feature sizes, yield will degrade due to the increased process variations. Thus, a key challenge is to improve the design and implementation practices to use as many as possible manufactured circuits even with physical defects. On the other hand, FPGA (Field Programmable Gate Array) devices continuously increase their market share compared to ASICs due to their potential for high performance and the ability to reconfigure their functionality on the field. Just like other lithographically produced chips, FPGAs suffer from production defects, but as they are routing dominated, defects are more likely found in the interconnect than in logic blocks. Nevertheless, the reconfigurability characteristic and the inherent redundancy of FPGAs have made possible to explore fault tolerance capabilities on them, suggesting that FPGAs are a good substrate to study architectures, methods and tools for fault tolerance so as to enable devices to function in spite of defects.
Our goal is to improve fault tolerance of designs mapped to FPGA devices by exploring computing architectures that make possible the implementation of applications by improving the robustness of the building blocks and bypassing the defective blocks. Our claim is that neuro-cellular computing is a promising way to address such problems, since they combine the adaptability and robustness of neural approaches while using the purely decentralized and scalable computation scheme of cellular models.
In this context, we first consider applications that would take advantage of neural building blocks, especially neural fields that have proved to possess a number of computational properties that make them good and natural candidates as elementary building blocks of complex architectures for various application domains such as perceptual tasks or autonomous robotics.
Following previous works of our research team where neural field models have been combined with stochastic arithmetic and cellular computing to define massively distributed, decentralized and scalable neural fields implemented on FPGAs, this PhD thesis will focus on improving the hardware fault tolerance of our models. In a first step of this research proposal, isotropic and fault tolerant routing schemes based on cellular reaction-diffusion mechanisms have to be defined, ensuring fault tolerance in the local communication between neurons without using costly hardware redundancy. In a second step, this thesis will consider the problem of communication between different neural fields (or maps). The basic feature of a neural architecture that uses several maps is to connect them with some topographically organized receptive fields, where each neuron of a map “seeing” a localized group of neurons in each afferent map. Implementing such a connectivity in a cellular substrate is challenging. Moreover, some property of re-organization of the receptive fields will have to be implemented so as to ensure a natural fault tolerance when assembling neural maps.
The candidate should have the equivalent of a Master in Computer Science, preferably in a specialty related to artificial intelligence and/or distributed numerical computation. Adequate knowledge of digital hardware design will be assessed, as well as experience in software design. The candidate must fluently speak English and/or French.
B. Girau and C. Torres-Huitzil, “Optimal weight storage improves fault tolerance of SOMs,” in International Joint Conference on Reconfigurable Computing and FPGAs ReConFig, 2017. A. Vazquez, Roberto, B. Girau, and J.-C. Quinton, “Visual attention using spiking neural maps,” in International JointConference on Neural Networks IJCNN, 2011. B. Chappet De Vangel, C. Torres-Huitzil, and B. Girau, “Randomly spiking dynamic neural fields,”Journal of EmergingTechnologies in Computing Systems, 2014. M. Sipper, “The emergence of cellular computing,” Computer, vol. 32, no. 7, pp.18–26, 1999.
Neural networks, neural fields, FPGA, digital hardware, fault tolerance